1. Technical Field
Embodiments of the present disclosure generally relate to a clock generation device and a semiconductor device including the same, and more particularly to a technology for tuning an internal clock to a desired frequency.
2. Related Art
Recently, with the increasing development of higher-speed electronic systems each having a semiconductor memory device, a skew between an external clock signal applied to the semiconductor memory device and output data of the semiconductor memory device is of importance to correct the transmission of data.
Generally, the semiconductor memory device includes an internal clock signal generation circuit configured to generate an internal clock signal synchronized with the external clock signal to minimize a resulting skew.
The conventional internal clock signal generation circuit may include an oscillator configured to generate an internal clock. However, if an error occurs according to a change in process, voltage, and/or temperature (PVT), it is impossible to adjust the clock signal using a target frequency.
In order to test the memory device, stand-alone-machine based test devices have been widely used.
However, if a pad or similar means capable of directly accessing the memory in the same manner as in either a memory device associated with a microprocessor or an embedded memory device, it is impossible to test the memory devices using the stand-alone-machine based test device. In order to address this issue, the scheme for including a Built-In Self Test (BIST) circuit into the semiconductor device has recently been proposed.
However, if an error occurs in a period or cycle of the oscillator according to a change in PVT, it becomes difficult to perform testing that is correct in the BIST circuit, such that there is a higher probability of overkill. Therefore, a method for properly tuning an internal clock generated from the oscillator of the internal clock signal generation circuit to a target clock is of importance.